In the related art, the integration degree of a semiconductor device has doubled every eighteen to twenty-four months according to Moore's law. However, a gate tunnel leakage current around the 90 nm node may not be disregarded, and thus a gate oxide film of MOSFET has almost completely stopped being thinned. In addition, since it is difficult to control the short channel effect, a reduction in the gate length has slowly progressed.
As a result, it is difficult to improve the performance of the MOSFET itself, engineering for mobility improvement has been performed using a mechanical stress such as DSL (Dual Stress Liner) or embedded SiGe on or beyond the 90 nm node. A mechanical stress technique considered in terms of manufacturing is substantially employed up to the 45 nm node. Beyond the 45 nm node, scaling of a gate oxide film has started to progress by heightening the dielectric constant of the gate oxide film with an HKMG structure using a high dielectric constant (HK: high-k) and metal gate (MG) electrode.
The HKMG structure is manufactured mainly using two kinds of methods such as gate-first and gate-last methods.
In the gate-first method, a poly-Si gate structure or an SiON gate insulating film structure in the related art is only replaced with the HKMG structure, and thus the structure is relatively simple.
On the other hand, in the gate-last method, a poly-Si dummy gate electrode structure which is initially formed is replaced with the HKMG structure after an interlayer insulating layer is removed (for example, refer to JP-A-2007-134432) . For this reason, the manufacturing method thereof is greatly different from that of a semiconductor device in the related art. There are many cases where, in the gate-last structure, metals having different work functions are employed in the NMOS and PMOS using the same high-k (HK) insulation layer. In addition, since very fine patterns are processed, the gate length which is patterned is desired to be arranged with regularity so as to be constant for ease of manufacturing.
Here, FIG. 14 shows a semiconductor device having the HKMG structure in the related art. In addition, FIG. 15 shows a gate-last manufacturing process as a manufacturing method of the semiconductor device having the HKMG structure in the related art.
The semiconductor device 60 shown in FIG. 14 includes, a semiconductor base 61 provided with a predetermined element separation and diffusion regions, gate electrodes 62 and 63 formed on the semiconductor base 61, and an interlayer insulating layer 64. The gate electrode 62 has a metal gate electrode 68 formed via an HK insulating layer 65, a Pfet WF (Work Function) metal layer 66, and an Nfet WF (Work Function) metal 67 on the semiconductor base 61. The gate electrode 63 has a metal gate electrode 68 formed via an HK insulating layer 65 and an Nfet WF (Work Function) metal 67 on the semiconductor base 61. Further, the gate electrode 62 and the gate electrode 63 have side wall spacers 69 formed at the side walls of the metal gate electrodes 68.
Next, a manufacturing method of the semiconductor device 60 shown in FIG. 14 will be described.
First, as shown in FIG. 15A, a gate insulating film 72 and a dummy gate electrode 71 are formed on the semiconductor base 61. The dummy gate electrode 71 is formed as follows. The gate insulating film 72 is formed on the semiconductor base 61 through, for example, dry oxidation (O2, 700° C.), and then a dummy gate electrode material layer is formed on the gate insulating film 72 using a CVD method or the like. In addition, a resist pattern is formed on the dummy gate electrode material layer using lithography. Anisotropic etching is performed for the gate insulating film 72 and the dummy gate electrode material layer using the resist as a mask, thereby forming the dummy gate electrode 71. At this time, since a very fine pattern is processed, the resist pattern which is formed on the dummy gate electrode material layer using the lithography is formed with a specific size for ease of manufacturing.
In addition, a Si3N4 layer or the like is formed using a plasma CVD method and then is etched back, thereby forming the side wall spacers 69 at the side walls of the dummy gate electrodes 71. Further, the interlayer insulating layer 64 is formed on the semiconductor base 61 so as to cover the dummy gate electrodes 71 and the side wall spacers 69, and is planarized using a CMP method.
Thereafter, as shown in FIG. 15B, the dummy gate electrodes 71 are removed using a dry etching method or a wet etching method, so as to open insides of the side wall spacers 69.
Further, as shown in FIG. 15C, the HK insulating layer 65, the Pfet WF metal layer 66, and the Nfet WF metal layer 67 are formed inside the grooves from which the dummy gate electrodes are removed. In addition, a low resistance gate material is buried in the grooves from which the dummy gate electrodes are removed, and the metal gate electrodes 68 are formed by planarizing the interlayer insulating layer 64 using a CMP method.
Through the above-described process, it is possible to manufacture the semiconductor device having the HKMG structure in the related art shown in FIG. 14.